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| PRELIMINARY PRODUCT SPECIFICATION 430MHz-950MHz Single Chip RF Transceiver FEATURES * * * * * * * * * True single chip GMSK/GFSK transceiver 433MHz, 868MHz and 915MHz LPRDbands compatible Multi-channel operation Easy 14-bit configuration 0 to 76.8kbit/s data rate Reliable communication due to superior adjacent channel selectivity No Manchester encoding of data required Few external components required Standby- and power down-mode NRF903 APPLICATIONS * * * * * * * * Alarm and Security Systems Automatic Meter Reading (AMR) Home Automation Remote Control Surveillance Wireless Handsfree Automotive Telemetry Toys Wireless Communications * * GENERAL DESCRIPTION NRF903 is a true single chip multichannel UHF transceiver designed to operate in the unlicensed 433MHz, 868MHz and 915MHz LPRD- (Low Power Radio Device) bands. It features both GMSK (Gaussian Minimum Shift Keying) and GFSK (Gaussian Frequency Shift Keying) modulation and demodulation capability at an effective bit rate of 76.8kbit/s for 153.6kHz channel bandwidths. Transmit power can be adjusted to a maximum of 10dBm. Antenna interface is differential and suited for low cost PCB-antennas. All necessary configuration data is programmed by a 14-bit configuration word via a Serial Peripheral Interface (SPI). Multi-channel operation and excellent receiver selectivity makes NRF903 suitable for wireless links where high-reliability is a key requirement. NRF903 operates from a single +3V DC supply and features power down- and standby-modes which makes power saving easy and efficient. As a primary application, the transceiver is intended for UHF radio equipment in compliance with the European Telecommunication Standard Institute (ETSI) specification EN 300 220-1 V1.2.1. and the US Federal Communications Commission (FCC) standard CFR47. QUICK REFERENCE DATA Parameter Frequency bands Value 433.05 - 434.87 868 - 870 902-928 0 -76.8 GMSK/GFSK 19.2 10 -100 >50 2.7 - 3.3 170 Unit MHz kbit/s kHz dBm dBm dB V - Bit rate Modulation Frequency deviation Max. RF output power @ 180, 3V Sensitivity @ 180, BR=76.8 kbit/s, BER<10-3 Adjacent channel selectivity Supply voltage Number of channels Table 1. NRF903 quick reference data. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 1 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver ORDERING INFORMATION Type number NRF903-IC NRF903-EVKIT Description 32 pin TQFP Evaluation kit with NRF903 IC Version A 1.0 Table 2. NRF903 ordering information. BLOCK DIAGRAM fs=4*fIF 10.7MHz Ceramic filter FILT2 VDD 8, 9, 14, 15, 31 1, 6, 7, 17, 23, 24, 27, 30, 32 FILT1 *) VSS 22 21 NRF903 TQFP32 IF-filter polyphase filter 18 GMSK/ GFSK demod. C_SENSE Dout Din mux LNA 28 ANT1 ANT2 29 PA 90o 19 DATA 12 Serial interface unit CS 10 11 CFG_DATA CFG_CLK Frequency synthesizer XOSC and VCO GMSK-modulator Transceiver control and configuration register IND1 IND2 13 16 2 3 4 5 20 25 26 LF1 LF2 CLK_OUT TXEN PWR_DWN STBY REFERENCE *) The external filter may be replaced with a 10nF capacitor at the expense of receiver performance (see page 13) Nordic VLSI ASA Revision: 1.0 11.0592MHz R1 R2 C2 C1 C3 L1 VDD L2 Cdecoupl LOOP FILTER Figure 1. NRF903 block diagram with external components. - Vestre Rosten 81, N-7075 Tiller, Norway Page 2 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver PIN FUNCTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 Name VSS LF1 LF2 IND1 IND2 VSS VSS VDD VDD CFG_CLK CFG_DATA CS Pin function Ground Output Input Input Input Ground Ground Power Power Input Input Input Description Ground (0V) Frequency synthesiser PLL loopfilter connection #1 Frequency synthesiser PLL loopfilter connection #2 External inductor for VCO External inductor for VCO Ground (0V) Ground (0V) Power supply (+3.0V DC) Power supply (+3.0V DC) Clock for programming mode (input) Serial input for transceiver configuration data Chip select CS = "0" transceiver normal operating mode CS = "1" transceiver programming mode Crystal oscillator input (11.0592MHz) Power supply (+3.0V DC) Power supply (+3.0V DC) Full swing clock for external microcontroller Output frequency is set by 2 bits in the configuration word fCLK_OUT=11.0592MHz/n, where n is 1,2,4 or 8 Ground (0V) Carrier sense Transmitted/received data Select transmit/receive mode TXEN = "0" Receive mode TXEN = "1" Transmit mode Input from 1st IF filter (external, 10.7MHz) to IF-amplifier IF output to 1st IF filter (external, 10.7MHz) Ground (0V) Ground (0V) Power down mode Refer to Table 5. for mode setup Standby mode Refer to Table 5. for mode setup Ground (0V) Antenna terminal Antenna terminal Ground (0V) Power supply (+3.0V DC) Ground (0V) 13 14 15 16 XC1 VDD VDD CLK_OUT Input Power Power Output 17 18 19 20 VSS C_SENSE DATA TXEN Ground Output Bidirectional Input 21 22 23 24 25 26 27 28 29 30 31 32 FILT2 FILT1 VSS VSS PWR_DWN STBY VSS ANT1 ANT2 VSS VDD VSS Input Output Ground Ground Input Input Ground Bidirectional Bidirectional Ground Power Ground Table 3. NRF903 pin functions. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 3 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver ELECTRICAL SPECIFICATIONS Conditions: VDD = +3V DC, VSS = 0V, TA= -40C to +85C Symbol VDD VSS t IDD Parameter (condition) Supply voltage Ground Operating temperature range Total current consumption: Receive mode : 433MHz : 868-928MHz Transmit mode @ -8 dBm RF power : 433MHz : 868-928MHz Transmit mode @ 10 dBm RF power : 433MHz : 868-928MHz Standby mode Power-down mode Number of available channels with fixed inductor 1) Modulation type Frequency deviation Bit rate Demodulated data jitter Startup-time Switching time (RX to TX, and TX to RX) Max. RF output power @ 180 load Sensitivity @ 180, BR=76.8kbit/s, BER < 10-3 Channel spacing Frequency synthesizer resolution Adjacent channel selectivity (ETSI definition) 2) Mirror image suppression Adjacent channel power (76.8kbit/s) Dynamic range Carrier sense input power trigger level 1st IF frequency 2nd IF frequency IF noise bandwidth Crystal frequency Crystal reference frequency stability requirement @ 433MHz, BR = 76.8kbit/s @ 868-928MHz, BR = 76.8kbit/s External micro-controller clock output frequency 3) Recommended antenna port differential impedance Spurious emission 4) Min. 2.7 -40 Typ. 3 0 27 18.5 22.5 16 25 31.5 41 200 Max. 3.3 +85 Units V V C mA mA mA mA mA mA A A 1 170 GFSK/GMSK 19.2 0 76.8 2.5 5 1.5 10 -100 153.6 153.6 50 28 35 -40 90 -106 10.7136 345.6 130 11.0592 40 20 11.0592 #CH f BR tj tstart tRX/TX PRF CHBW fres ACS MIS ACPGMSK DR PC_SENSE fIF1 fIF2 BWIF fXTAL kHz kbit/s s ms ms dBm dBm kHz kHz dB dB dBc dB dBm MHz kHz kHz MHz fP_CLK ZI ppm ppm 1.3824 MHz 180 Compliant with ETSI EN 300-220-1 V1.2.1 And FCC CFR47 Table 4. nRF0903 electrical specifications. 1): Use must be according to ETSI- and FCC frequency regulations 2): Refer to chapter Adjacent channel selectivity (ACS) on page 17 for definition 3): fP_CLK may be set to 1.3824MHz, 2.7648MHz, 5.5296MHz or 11.0592MHz depending on configuration word 4): Antenna and matching network must be according to recommendations Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 4 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver ABSOLUTE MAXIMUM RATINGS Supply voltages VDD............................................ - 0.3V to +6V VSS ............................................................... 0V Input voltage VI....................................- 0.3V to VDD + 0.3V Output voltage VO ..................................- 0.3V to VDD + 0.3V Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device. Power dissipation PD (TA=25C).........................................300mW Temperatures Operating Temperature....... .... -40C to +85C Storage Temperature...... ...... -55C to +125C ATTENTION! Electrostatic Sensitive Device Observe Precaution for handling PIN ASSIGNMENT PWR_DWN 25 24 VDD ANT2 ANT1 VSS VSS VSS 27 32 31 30 29 28 26 VSS LF1 LF2 IND1 IND2 VSS VSS VDD STBY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS VSS FILT1 FILT2 TXEN DATA C_SENSE VSS NRF903 32 pin TQFP 23 22 21 20 19 18 17 CFG_DATA Figure 2. NRF903 pin assignment. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 5 of 24 - CLK_OUT CFG_CLK VDD VDD VDD XC1 CS Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver PACKAGE OUTLINE NRF903, 32 pin TQFP. (Dimensions in mm.) D D1 32 1 2 3 4 31 30 29 28 27 26 25 24 23 22 21 20 19 b E E1 5 6 7 8 9 10 11 12 13 14 15 16 e 18 17 A A2 A1 L Package Type 32 pin TQFP Min Max E1/D1 7.00 E/D 9.00 A 1.60 A1 0.05 0.15 A2 1.35 1.45 e 0.80 b 0.30 0.45 L 0.45 0.75 0 7 Copl. 0.10 Figure 3. TQFP32 Package outline. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 6 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver APPLICATION INFORMATION User interface Figure 4 shows the user interface of NRF903. It consists of a total of 7 digital input/output pins. The interface is divided into two main functions; configuration and mode-control. In addition to these 7 pins, two extra signals are available; C_SENSE and CLK_OUT. C_SENSE is '0' when no carrier is detected in the received channel, '1' when a carrier with power level > -106dBm is detected. CLK_OUT is the full-swing 11.0592MHz reference frequency divided by 1,2,4 or 8. pin 19 pin 20 pin 26 pin 25 pin 11 pin 10 SPI-configuration Mode control DATA TXEN STBY PWR_DWN CFG_DATA CFG_CLK CS C_SENSE CLK_OUT NRF903 pin 12 pin 18 pin 16 Figure 4. NRF903 user interface Configuration is performed by clocking a 14-bit configuration word into a shift-register (see Table 6). These 14 bits are decoded into the corresponding frequency band, channel, output power and output clock frequency. The Serial Peripheral Interface (SPI) consists of the pins CFG_DATA, CFG_CLK and CS. Once configured, these pins are not used unless one or more of the parameters above need to be changed. Modes of operation Mode-control is set by the pins TXEN, STBY and PWR_DWN. Table 5 shows the operating mode according to signal settings. NRF903 operating mode Normal operation: Receive mode Normal operation: Transmit mode Power-down mode: No circuitry active Standby mode: Only XOSC- and Pin 16 (CLK_OUT) active. CLK_OUT frequency is 11.0592MHz before configuration Default mode*: SPI-unit override, 868MHz, Receive mode, Channel #0, 1.3824MHz output clock frequency Default mode*: SPI-unit override, 868MHz, Transmit mode, Channel #0, 10dBm output power, 1.3824MHz output clock frequency *: See chapter Transceiver configuration, page 9 STBY 0 0 0 1 PWR_DWN 0 0 1 0 TXEN 0 1 X X 1 1 0 1 1 1 Table 5. NRF903 operational mode as a function of external signals STBY, PWR_DWN and TXEN. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 7 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Transceiver configuration A total of 4 parameters are set by the user in an internal 14-bit configuration register. Table 6 shows the contents of the register. Bit 13 is the most significant bit (MSB). Bit 0-1 Parameter Frequency band Channel center position (Channel number) Output power P-external clock frequency output Total configuration data package size Symbol FB Description "00" Frequency band = 433.92 0.87 MHz "01" Frequency band = 869 1 MHz "10" Frequency band = 915 13 MHz "11" Not in use fcentre_433MHz = 433.152106 + CH 153.6103 [Hz] fcentre_868MHz = 868.1856106 + CH 153.6103 [Hz] fcentre_915MHz = 902.0928106 + CH 153.6103 [Hz] Output power setting Output power -8dBm + 6dBm POUT [dBm] "00" P system clock = fX-tal MHz "01" P system clock = fX-tal/2 MHz "10" P system clock = fX-tal/4 MHz "11" P system clock = fX-tal/8 MHz #bit 2 2-9 10-11 12-13 CH POUT fP_clk 8 2 2 14 Table 6. NRF903 Configuration word Transceiver parameters are clocked into the data shift register in the internal configuration unit by using the three-pin serial interface consisting of CS, CFG_CLK and CFG_DATA. Chip select (CS) is used to enable the transceiver configuration mode. Figure 5 illustrates the serial interface block diagram. Internal tranceiver control and config. register Decoding unit CFG_DATA CFG_CLK CS pin 11 pin 10 pin 12 Data shift register Figure 5. Serial Pheripheral Interface (SPI) for chip configuration During configuration, CS is activated and the configuration word is clocked in with the MSB first. After the configuration word has been clocked into the shift register, CS is deactivated and the new configuration setup is initialised. Timing diagram is shown in Figure 6. CFG_DATA bitrate may not exceed 1Mbps. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 8 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Once configured, device behaviour is set by the external signals TXEN, PWR_DWN, STBY and DATA (DATA is an input pin in transmit-mode, output in receive-mode). Configuration may be performed in all modes except standby- and power down mode. Register contents is still valid after power down and standby mode operation. Configuration data is lost only when supply voltage has been removed. CFG_CLK CS CFG_DATA MSB 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0 CFG_CLK CS CFG_DATA 13 Configuration mode enabled Bit 13 read into config. register 12 Figure 6. Timing diagram for chip configuration A preprogrammed channel (868.1856MHz) is available without using the SPI-configuration procedure. While in default mode (ref. Table 5.), the 868.1856MHz channel is activated with maximum power setting and an output clock frequency of 1.3284MHz. This feature has been included to ease debugging of micro-controller software. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 9 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Configuration example: A 868MHz system module is to be designed. The operating channel of the unit is channel #5. The transceiver units are operating within a small confined area. System channel organisation and ETSI frequency allocations are shown in Figure 7. 25KHz channel spacing band Channel #2 Channel #3 Low Duty-Cycle Band (<10%) Channel #0 Channel #1 Very Low Duty-Cycle Band (<1%) Channel #4 Channel #5 Channel #6 868.0 868.1 868.2 868.3 868.4 868.5 868.6 868.7 868.8 868.9 869.0 869.1 869.2 f [MHz] Figure 7. 868MHz LPRD-band, channel organisation The same crystal is shared by the micro-controller and transceiver. When applying power, NRF903 is set to Standby-mode (STBY = '1', PWR_DWN = '0'), a 11.0592MHz system clock is then available to the micro-controller at the CLK_OUT-pin after 0.9 ms (see Table 13). The micro-controller then sets the transceiver to normal operation, receive mode (STBY = '0', PWR_DWN = '0', TXEN = '0') for configuration (Receive mode is chosen during configuration in order to avoid unintentional transmission at an unwanted frequency). The configuration word is calculated as follows (refer to Table 6); 1. Setting frequency band: The system operates in the 868MHz LPRD-band, and FB is thus set to 01b. 2. Calculating channel frequency location: The center frequency of Channel #5 is 868.9536MHz. CH is found by solving for CH in the equation given in Table 6; CH = (fcentre_868MHz - 868.1856106)/ 153.6103 CH=5 (0000101b) 3. Setting output power The operational range is limited, and the output power is therefore reduced to a minimum in order to minimise current consumption in transmit mode. Pout is set to 0 (00b), resulting in an output power of -8dBm. 4. Setting the external microprocessor frequency A microprocessor that can perform all system functions at a system clock frequency of at least 4MHz is used. fP_clk is therefore set to 01b, resulting in a clock frequency of 5.5296MHz. The resulting 14-bit configuration word is then; (01 00 0000101 01b) where MSB is the leftmost bit. The configuration word is clocked in according to Figure 6. On the falling edge of CS, the internal decoding unit sets the frequency synthesiser to the wanted frequency. 4.1ms must be allowed for the synthesiser to stabilise before data may be demodulated (see Table 13). Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 10 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Timing information Table 13 contains the critical timing information for the NRF903 transceiver. The listed values in Table 13 assume the device has been configured. Configuration time is equal to (141/fCFG_DATA). This time must be added if the device is configured when the operation mode changes below are initiated. Mode/operation Power down* Receive Standby Receive Power down* Transmit Standby Transmit Transmit Receive Receive Transmit Power down* Standby fCFG_DATA tjitter (Recovered data) *: Same as applying power (VDD) when set to Receive/Transmit/Standby-mode Max. 5.0 4.1 5.0 4.1 1.5 1.5 0.9 1 2.5 Unit ms ms ms ms ms ms ms MHz s Table 13. Timing data for NRF903 Power down (Standby) Receive: The time required for correct demodulated data to appear at the DATA-pin when the device is set from power down (standby) mode to receive mode. Power down (Standby) Transmit: The time required for a correct transmitted data spectrum to appear at the ANT1- and ANT2pins when the device is set from power down (standby) mode to transmit mode. Transmit Receive: The time required for correct demodulated data to appear at the DATA-pin when the device is set from transmit mode to receive mode. Receive Transmit: The time required for a correct transmitted data spectrum to appear at the ANT1- and ANT2pins when the device is set from receive mode to transmit mode. Power down Standby: The time required until a stable reference clock signal is available at the CLK_OUT-pin when the device is set from power down mode to standby mode. fCFG_DATA: Configuration clock frequency. May be chosen arbitrary. tjitter: Transition flank peak jitter of demodulated data Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 11 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Antenna input/output The ANT1 and ANT2 pins provide RF input to the LNA (Low Noise Amplifier) when NRF903 is in receive mode, and RF output from the PA (Power Amplifier) when NRF903 is in transmit mode. The antenna connection to NRF903 is differential and the recommended load impedance at the antenna port is 180. Figure 14 shows a typical application schematic with a differential loop antenna on a Printed Circuit Board (PCB). The output stage (PA) consists of two open collector transistors in a differential pair configuration. VDD to the PA must be supplied through the collector load. When connecting a differential loop antenna to the ANT1/ANT2 pins, VDD should be supplied through the centre of the loop antenna as shown in Figure 14. A single ended antenna or 50 test instrument may be connected to NRF903 by using a differential to single ended matching network (BALUN) as shown in Figure 8. VDD Lch RF in/out 50 ohm ANT1 Cs1 NRF903 ANT2 Lp Cs2 Figure 8. Connecting the NRF903 to a single ended antenna by using a differential to singleended matching network. The RF-choke inductor to VDD in Figure 8, needs to have a Self Resonance Frequency (SRF) above the transmit/receive frequency to be effective. Suitable component values are listed in Table 7. Frequency band [MHz] 433.92 0.87 869 1 915 13 Lp [nH] 27 10 Lch [nH] 68 39 Cs1 [pF] 10 3.3 Cs2 [pF] 10 3.3 Table 7. Single-ended matching network components values for NRF903 An additional notch filter (L and C) at the 50 RF input/output may be necessary dependent on the application requirements. For 433MHz use, see application note nAN400-05. (868/915MHz use; application note not currently available) A single ended antenna may also be connected to NRF903 using an 4:1 impedance RF transformer. The RF transformer must have a centre tap at the primary side for VDD supply. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 12 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver PLL loop filter The synthesizer loopfilter is an external, single-ended third order lag-lead filter as shown in Figure 9. The recommended filter component values are listed in Table 8. LF1 (2) R1 LF2 (3) R2 C2 C1 C3 Figure 9. Loopfilter configuration Frequency band [MHz] 433.92 0.87 869 1 915 13 C1 [pF] 180 330 C2 [pF] 12 22 C3 [nF] 0.82 1.5 R1 [k] 1200 560 R2 [k] 180 100 Table 8. Loopfilter components values for NRF903 RF output power Output power is set by bit 10 and 11 in the configuration word (Ref. Table 6.). A total of 4 different settings are available; 10dBm, 4dBm, -2dBm and -8dBm. Figure 10 shows the total chip DC current consumption plotted as a function of power level setting and frequency band. Antenna matching according to recommendations is assumed. Total Chip Current 45 Current Consumption [mA] 40 35 30 25 20 15 -8 -8 -8 433 MHz 868-928 MHz 10 4 -2 4 -2 -2 4 10 10 Power setting [dBm] Figure 10. Total current consumption vs. power setting (typical values) Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 13 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Critical components Below are listed suggested components and vendors for the most critical external components for NRF903. It should be noted that these are suggestions only, and that other vendors may offer compatible components. Availability, price and delivery times may differ for the different vendors. Inductors (L1, L2) Operated in the 433 MHz range, the following 39nH (2%) inductors (0603) are suitable for use with NRF903. Vendors Pulse Coilcraft muRata WWW address www.pulseeng.com www.coilcraft.com www.murata.com Part. no., 39 nH inductors, 0603 size PE-0603CD390GTT 0603CS-39NXGBC LQW1608A39NG00 Table 9a. Vendors and part no. for suitable inductors (433MHz operation). Operated in the 868/915MHz range, the following 6.8nH inductors (0603) are suitable for use with NRF903. The Pulse and Coilcraft inductors have 2% tolerance, whilst the Murata inductor has 0.2nH tolerance. Vendors Pulse Coilcraft muRata WWW address www.pulseeng.com www.coilcraft.com www.murata.com Part. no., 6.8 nH inductors, 0603 size PE-0603CD060GTT 0603CS-6N8XGBC LQW1608A6N8C00 Table 9b. Vendors and part no. for suitable inductors (868/915MHz operation). 10.7MHz Ceramic filter The external 1st IF-filter is a piezoelectric ceramic filter with 330 input/output impedance. Center frequency should be positioned at 10.7MHz, and bandwidth should not be less than the channel spacing. 180kHz is a suitable bandwidth. Note that variations in absolute center frequency and bandwidth may differ for different vendors. Vendors muRata TDK WWW address www.murata.com www.tdk.co.jp Part. no. 10.7MHz filter, 180kHz bandwidth SFECV10.7MS3S-A-TC (SMD-package) FFE1070MS (Through-mount) Table 10. Vendors and part no. for suitable 10.7MHz ceramic filters. This filter may be replaced with a 10nF capacitor between the FILT1- and FILT2-pins, at the expense of sensitivity (approx. 3dB degradation) and adjacent channel selectivity. In this case, only the internal (second) IF-filter is used. Note that the image frequency resulting from the second mixing will then appear in the baseband. This image is centered at 691kHz above the signal of interest. Table 11 shows the degradation of receiver ACS without the use of the ceramic filter. Degradation will be more evident for channels spaced further from the center channel. ACS definition ETSI Real* 0 ppm frequency offset Upper channel Lower channel [dB] [dB] 11.3 15.2 0.9 6.2 20 ppm frequency offset Upper channel Lower channel [dB] [dB] 7.8 10.8 1.3 4.3 *: 868/915 MHz, GMSK signal, 76.8 kbit/s, 19.2 kHz deviation Table 11. ACS degradation without external ceramic 10.7 MHz filter (typical) Nordic VLSI ASA Revision: 1.0 Vestre Rosten 81, N-7075 Tiller, Norway Page 14 of 24 Phone +4772898900 Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver 11.0592MHz Crystal reference When specifying crystal, keep in mind that the frequency deviation requirement is 20ppm for 868/915MHz operation and 40ppm for 433MHz operation. This accounts for both frequency tolerance (f/f) and temperature variations in the crystal frequency. Example; For a 868MHz system, a crystal frequency tolerance (f/f) of 15ppm, leaves 5ppm for drift due to temperature variations. As temperature characteristics are closely related to crystal cost, it is advisable not to exaggerate the crystal specification. Note that it is the maximum relative difference between the receiver and transmitter reference frequency that set the crystal oscillator requirement. If the transmitter and receiver will not be operating at opposite temperature extremes at the same time (maximum difference), the requirements towards temperature characteristics may be relaxed accordingly. The key parameters for the NRF903 crystal reference is as follows; fc=11.0592MHz C0,max=7pF CL=12pF (Note that PCB routing load must be included in CL) ESRmax=60 Vendors Epson Raltron Golledge Fox Electronics Jauch WWW address www.epson-electronics.de www.raltron.com www.golledge.com www.foxonline.com www.jauch.de Part. no., SMD-package MA-406H SA-315H / 315HZ H10S GSX-2 FD JXS 75 Table 12. Vendors and part no. for suitable 11.0592MHz crystals Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 15 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Data modulation The DATA pin is the input to the digital modulator of the transmitter while in TX-mode, and demodulated data output while in receive-mode. The input signal to this pin should be standard CMOS logic levels at data rates up to 76.8kbit/s. No encoding of data is required. The demodulated digital output data appear at the DATA-pin at standard CMOS logic levels. NRF903 uses GMSK/GFSK modulation of data for optimum modulation bandwidth efficiency. This type of modulation is an enhanced version of FSK in which each of the two logic levels corresponds to a frequency value; DATAFSK = "1" f'1' = fcentre + f DATAFSK = "0" f'0' = fcentre - f In Gaussian Frequency Shift Keying (GFSK), the data is filtered through a gaussian filter before modulating the carrier. Figure 11 shows the general principle. This results in a narrower power spectrum of the modulated signal, which in turn allows a higher bitrate to be transfered in the same channel bandwidth. Figure 12 shows the difference between a 76.8kbit/s GMSK- and FSK-spectrum. Gaussian Minimum Shift Keying (GMSK) is the term used for a GFSK signal where the bitrate is four times the frequency deviation. DATA logic level '1' '0' time frequency f'1' 19.2kHz fcentre 19.2kHz f'0' time Figure 11. Principle of Gaussian filtering of transmitted data a) GMSK spectrum b) FSK spectrum Figure 12. Power Density Spectrum (PDS) of a GMSK- and FSK-signal (f = 19.2kHz, BR = 76.8kbit/s, BTGMSK = 0.5) Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 16 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Mirror image suppression A cost-saving feature of the NRF903 transceiver is on-chip mirror image cancellation. All heterodyne receivers have a mirror image frequency for a given channel, which may cause inband interference. The NRF903 mirror image frequency is always positioned 21.4MHz below the received channel, regardless of channel number or frequency band. As the NRF903 mirror image is attenuated by use of an on-chip quadrature cancellation technique, a costly external SAW/crystal-filter may be avoided. Typical attenuation of the mirror image frequency is 35dB. Adjacent channel selectivity (ACS) NRF903 is a true multi-channel transceiver, enabling simultaneous operation of NRF903 devices in the same environment. This is possible due to high-Q filtering of the received channel to attenuate the interference resulting from neighbouring channels. Channel filtering is performed by the external 10.7MHz filter combined with an internal band-pass filter. The adjacent channel selectivity of the receiver is defined by ETSI as the ability to demodulate a received signal at the sensitivity limit, with the presence of a sine component centered in the adjacent channel (see Figure 13). Note that the ETSI definition is merely ment as a comparative figure. The system ACS is always lower, as the adjacent channel is not likely to be a sine component, but a modulated spectrum. +/- 20ppm frequency drift in receiver X-tal Adjacent channel attenuation Channel #-1 Channel #0 Channel #+1 Figure 13. Adjacent channel power attenuation obtained due to IF-filter passband characteristic (ETSI-def.) For comparison, the adjacent channel selectivity results for the NRF903 receiver is shown in Table 14. Both the upper and lower adjacent channels are listed due to the filter transfer function not being symmetric. If the datarate is reduced, performance will be further enhanced due to reduced bandwidth of the transmitted signal. ACS improves for channels spaced further away from the received channel. Reference frequency stability is a parameter that influences the resulting ACS. Deviation from the ideal frequency will result in a corresponding deviation of the transmitted center frequency for a transmitter, and an IF offset for the receiver. This will appear as an offset in the the IF-filter center frequency (see Figure 13). Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 17 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver ACS definition ETSI Real* 0 ppm frequency offset Upper channel Lower channel [dB] [dB] -51.1 -66.4 -37.4 -35.0 20 ppm frequency offset Upper channel Lower channel [dB] [dB] -40.0 -50.5 -27.0 -25.4 *: 868/915MHz, GMSK signal, 76.8kbit/s, 19.2kHz deviation Table 14. Adjacent channel selectivity for the NRF903 receiver NOTE: 20ppm frequency deviation corresponds to approx. 20kHz for the 868/915MHz frequency bands, whilst only 10kHz at 433MHz. The ACS-performance listed in Table 14 will thus be much better for 433MHz operation as the channel bandwidth is identical for all three frequency bands. This implies that a 40ppm crystal may be used for 433MHz operation and still achive the same performance as listed in Table 14. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 18 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver APPLICATION SCHEMATIC R3 18K C12 4.7pF C13 4.7pF VDD C11 33pF C14 4.7pF J1 Loop Antenna 9.5x9.5mm VDD R1 R2 100K 560K C10 4.7nF C9 33pF STBY PWR_DWN 32 31 30 29 28 27 26 25 VSS VDD VSS ANT2 ANT1 VSS STBY PWR_DWN C3 1.5nF C1 330pF C2 22pF C4 33pF L1 6.8nH VDD L2 6.8nH VDD C5 4.7uF U1 NRF903 C6 4.7nF VDD CFG_CLK CFG_DATA CS XC1 VDD VDD CLK_OUT 1 2 3 4 5 6 7 8 VSS LF1 LF2 IND1 IND2 VSS VSS VDD NRF903 VSS VSS FILT1 FILT2 TXEN DATA C_SENSE VSS 24 23 22 21 20 19 18 17 1 2 F1 10.7MHz aaaaaaaa 9 10 11 12 13 14 15 16 VDD C7 33pF C8 4.7nF CFG_CLK CFG_DATA CS X1 11.0592MHz Figure 14. NRF903 application schematic. Component C1 Description X7R ceramic chip capacitor, (PLL loop filter); @ 433MHz @ 868-928MHz X7R ceramic chip capacitor, (PLL loop filter); @ 433MHz @ 868-928MHz X7R ceramic chip capacitor, (PLL loop filter); @ 433MHz @ 868-928MHz NP0 ceramic chip capacitor, (Supply decoupling) Tantalum chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) X7R ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Supply decoupling) NP0 ceramic chip capacitor, (Antenna tuning)* NP0 ceramic chip capacitor, (Antenna tuning) * NP0 ceramic chip capacitor, (Antenna tuning) * VCO inductor (see critical components section); Q>40 @ 433MHz Q>40 @ 868-928MHz VCO inductor (see critical components section); Q>40 @ 433MHz Q>40 @ 868-928MHz 0.1W chip resistor, (PLL loop filter) @ 433MHz @ 868-928MHz 0.1W chip resistor, (PLL loop filter) @ 433MHz @ 868-928MHz 0.1W chip resistor, (Antenna Q reduction) * Ceramic filter (see critical components section) Crystal (see critical components section) Size 0603 3 TXEN DATA C_SENSE CLK_OUT Value 330 Tol. 10% 10% 10% 5% 20% 10% 5% 10% 5% 10% 5% 0.1 0.1 0.1 2% 2% 1% 1% 1% Units pF C2 0603 22 pF C3 0603 0603 3216 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 1.5 33 4.7 4.7 33 4.7 33 4.7 33 4.7 4.7 4.7 39 6.8 39 6.8 560 nF pF F nF pF nF pF nF pF pF pF pF nH C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 L1 L2 0603 nH R1 0603 k R2 0603 0603 - 100 18 10.7 11.0592 k k MHz MHz R3 F1 X1 Table 15. Recommended External Components. *: 868MHz operation (For 433MHz and 915MHz use, please refer to application notes nAN400-05 and nAN900-02) Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 19 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver PCB layout and decoupling guidelines A well-designed PCB is necessary to achieve good RF performance. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The NRF903 DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors, see Table 15. It is preferable to mount a large surface mount capacitor (e.g. 2.2F ceramic) in parallel with the smaller value capacitors. The NRF903 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the NRF903 IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes in or close to the VSS pads. Preferably one via hole should be used for each VSS pin. Full swing digital data or control signals should not be routed close to the PLL loop filter components, the external VCO inductors or the power supply lines. The VCO inductors placement is important. Optimum placement of the VCO inductors yields a PLL loop filter voltage of 1.1 0.2V, which can be measured at LF2 (pin 3). Figure 15 shows the recommended layout and inductor placement for a PCB compatible with all three frequency bands. For 915MHz operation, the inductors should be placed according to Figure 15 a., and for 433MHz and 868MHz operation as shown in Figure 15 b. IND1 IND1 IND2 IND2 VSS L2 VSS VSS L1 L1 L2 VDD a) 915 MHz VDD b) 433/868 MHz Figure 15. Inductor placement for 915MHz and 433/868MHz operation. PCB layout example Figure 16 shows a PCB layout example for the application schematic in Figure 14. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a continuous ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane. There is no ground plane beneath the antenna. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 20 of 24 - Phone +4772898900 VSS LF1 LF1 LF2 LF2 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver a) Top silk screen b) Bottom silk screen c) Top view d) Bottom view Figure 16. PCB layout (example) for NRF903 with loop antenna. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 21 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver DEFINITIONS Data sheet status Objective product specification Preliminary product specification Product specification This datasheet contains target specifications for product development. This datasheet contains preliminary data; supplementary data may be published from Nordic VLSI ASA later. This datasheet contains final product specifications. Nordic VLSI ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Table 16. Definitions. Nordic VLSI ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic VLSI does not assume any liability arising out of the application or use of any product or circuits described herein. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic VLSI ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic VLSI ASA for any damages resulting from such improper use or sale. Product specification: Revision Date: 05.02.2001. Datasheet order code: 050201NRF903 All rights reserved (R). Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 22 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver YOUR NOTES Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 23 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 PRELIMINARY PRODUCT SPECIFICATION NRF903 Single Chip RF Transceiver Nordic VLSI - World Wide Distributors For Your nearest dealer, please see http://www.nvlsi.no Main Office: Vestre Rosten 81, N-7075 Tiller, Norway Phone: +47 72 89 89 00, Fax: +47 72 89 89 89 E-mail: nRF@nvlsi.no Visit the Nordic VLSI ASA website at http://www.nvlsi.no Nordic VLSI ASA Revision: 1.0 - Vestre Rosten 81, N-7075 Tiller, Norway Page 24 of 24 - Phone +4772898900 - Fax +4772898989 January 2001 |
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